Results 1 to 4 of 4

Thread: Error 10476

  1. #1
    Join Date
    May 2018
    Posts
    4
    Rep Power
    1

    Question Error 10476

    In this code at the time of compilation a 10476 error shows up. The code is:

    -- convertidor BCD a 7 segmentos
    library ieee;
    use ieee.std_logic_1164.all;

    -- definicion de la entidad

    entity convertidor7 is
    port (A: in std_logic_vector (1 downto 0);
    B: in std_logic_vector (1 downto 0);
    C: in std_logic_vector (1 downto 0);
    D: in std_logic_vector (1 downto 0);
    adisplay,bdisplay,cdisplay,ddisplay,edisplay,fdisp lay,gdisplay: out std_logic);
    end convertidor7;

    -- definicion de las seņales de entrada / salida

    architecture bolean of convertidor7 is
    signal An,Bn,Cn,Dn,anda1_out,anda2_out,anda3_out,anda4_ou t,andb1_out,andb2_out,andb3_out,andb4_out,
    andc1_out,andc2_out,andc3_out,andc4_out,andd1_out, andd2_out,andd3_out,andd4_out,andd5_out,
    ande1_out,ande2_out,andf1_out,andf2_out,andf3_out, andf4_out,andg1_out,andg2_out,andg3_out,andg4_out: std_logic;

    -- fin de definicion de las seņales
    -- inicio de programa principal

    begin

    An <= not A(1);
    Bn <= not B(1);
    Cn <= not C(1);
    Dn <= not D(1);

    -- a

    anda1_out <= C and An; <=== this is the error
    anda2_out <= An and B and D;
    anda3_out <= Bn and Cn and Dn;
    anda4_out <= A and Bn and Cn;

    adisplay <= anda1_out or anda2_out or anda3_out or anda4_out;

    -- b

    andb1_out <= An and Bn;
    andb2_out <= An and Cn and Dn;
    andb3_out <= An and C and D;
    andb4_out <= A and Bn and Cn;

    bdisplay <=andb1_out or andb2_out or andb3_out or andb4_out;

    -- c

    andc1_out <= An and B;
    andc2_out <= An and D;
    andc3_out <= Bn and Cn and Dn;
    andc4_out <= A and Bn and Cn;

    cdisplay <= andc1_out or andc2_out or andc3_out or andc4_out,

    -- d

    andd1_out <= An and C and Dn,
    andd2_out <= An and Bn and C;
    andd3_out <= Bn and Cn and Dn;
    andd4_out <= A and Bn and Cn;
    andd5_out <= An and B and Cn and D;

    ddisplay <= andd1_out or andd2_out or andd3_out or andd4_out or andd5_out;

    -- e

    ande1_out <= An and C and Dn;
    ande2_out <= Bn and Cn and Dn;

    edisplay <= ande1_out or ande2_out;

    -- f

    andf1_out <= An and B and Cn;
    andf2_out <= An and Cn and Dn;
    andf3_out <= An and B and Dn;
    andf4_out <= A and Bn and Cn;

    fdisplay <= andf1_out or andf2_out or andf3_out or andf4_out;

    -- g

    andg1_out <= An and C and Dn;
    andg2_out <= An and Bn and C;
    andg3_out <= An and B and Cn;
    andg4_out <= A and Bn and Cn;

    gdisplay <= andg1_out or andg2_out or andg3_out or andg4_out;

    end bolean;

    The error states:

    Error (10476): VHDL error at BCD7SEG.vhd(34): type of identifier "C" does not agree with its usage as "std_ulogic" type


    Could anybody help me? A do not see why

    Thanks

  2. #2
    Join Date
    Mar 2016
    Posts
    11
    Rep Power
    1

    Default Re: Error 10476

    C is a std_logic_vector and anda1_out, An are std_logic

  3. #3
    Join Date
    May 2018
    Posts
    4
    Rep Power
    1

    Default Re: Error 10476

    Thank you!

  4. #4
    Join Date
    May 2018
    Posts
    4
    Rep Power
    1

    Default Re: Error 10476

    Thank you very much!

Similar Threads

  1. FPGA Counter Catch Eight game(error 10476, error 10558)
    By Prakash1201 in forum General Altera Discussion
    Replies: 5
    Last Post: September 14th, 2016, 05:32 AM
  2. Error (209053): Unexpected error in JTAG server -- error code 89
    By Wided HECHKEL in forum Quartus II and EDA Tools Discussion
    Replies: 0
    Last Post: April 13th, 2016, 04:42 AM
  3. Replies: 1
    Last Post: March 12th, 2012, 12:36 AM
  4. Error: Unexpected error in JTAG server -- error code 35
    By ZioFester in forum FPGA, Hardcopy, and CPLD Discussion
    Replies: 1
    Last Post: October 18th, 2011, 10:57 PM

Tags for this Thread

Bookmarks

Posting Permissions

  • You may not post new threads
  • You may not post replies
  • You may not post attachments
  • You may not edit your posts
  •