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Thread: boot NIOS and FPGA from EPCS flash

  1. #21
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    Default Re: boot NIOS and FPGA from EPCS flash

    1)It's a development board(DE0-Nano Development and Education Board).
    2) In altera_epcq_controller_core.vhd i can see signals below that correspond to the serial ones.

    epcq_dclk : out std_logic; -- conduit_epcq_dclk
    epcq_scein : out std_logic_vector(0 downto 0); -- conduit_epcq_scein
    epcq_sdoin : out std_logic_vector(0 downto 0);
    epcq_dataout : in std_logic_vector(0 downto 0) := (others => '0'); -- epcq_dataout.conduit_epcq_dataout

    I still have a doubt how i can configure Dual purpose pins of DCLK,nCEO and ... If there are configured as regular I/O, i can't boot both hardware and software.
    I had to configure DCLK and nCEO as programming pin and DATA[0] and nCSO as compiler configured. I didn't find any datasheet about how to do that.
    I seems to be different with the other version of Quartus, because the serial signals were exported not the case with Quartus 15.0.

  2. #22
    Daixiwen is offline Moderator **Forum Master**
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    Default Re: boot NIOS and FPGA from EPCS flash

    I'm only using an outdated version of Quartus so I don't know what the exact settings are now.
    On my Cyclone IV / SOPC Builder project the EPCS controller exports the serial signals out of the SOPC component and they are connected to the correct pins in my top-level file. All four of them are configured as "regular I/O" for all four of them.
    But again, if you get the correct information from the flash (number of blocks, block size) it means that at one point the controller did get a valid reply from the EPCS chip with an ID, so I think that this part is working.

    I don't know the DE0-nano kit but do you have some example designs with the kit? If yes you can try and open them in Quartus and see how they connected them.
    Definition of a man-year: 730 people trying to finish the project before lunch

  3. #23
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    Default Re: boot NIOS and FPGA from EPCS flash

    Last time I looked at the HAL code for bit-banging epcq it always does an erase before a write.
    So your writes have to cover a full flash sector.

    That HAL code is a typical Altera example of making something that should be a few 100
    instructions into kilobytes of code that doesn't let you do anything other than the precise
    action that some class/tutorial reqired.

  4. #24
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    Default Re: boot NIOS and FPGA from EPCS flash

    Hi again,

    Sorry for my long absence, i was on vacation.
    My problem is resolved now, I just changed the clock source of the EPCS CONTROLLER. The clock was driven from the system clock using a CLOCK BRIDGE.
    Now, the clock is driven from a PLL OUTPUT ( the system and the EPCS CONTROLLER clocks are now independent).
    Thank you Daixiwen & dsl for helping me.

    Best regards,

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