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Forum: SoC Device Discussion

Discussion of all the SoC devices including FPGA and HPS interaction

  1. Sticky Thread Sticky: SoC Dev Kit Quality of Experience Survey

    Started by BadOmen, October 14th, 2014 04:36 PM
    • Replies: 0
    • Views: 13,161
    October 14th, 2014, 04:36 PM Go to last post
  2. Sticky Thread Sticky: !!!! Read Me !!!!

    Started by BadOmen, July 19th, 2013 03:37 PM
    • Replies: 0
    • Views: 32,284
    July 19th, 2013, 03:37 PM Go to last post
  1. sopc2dts gives dts with 64bit address.

    Started by megahraj.ag, November 14th, 2017 12:45 AM
    arria10, device tree
    • Replies: 0
    • Views: 101
    November 14th, 2017, 12:45 AM Go to last post
  2. Question Write/Read RAM memory from FPGA.

    Started by skliarovartem, November 11th, 2017 06:16 PM
    incip_memory2
    • Replies: 3
    • Views: 212
    November 12th, 2017, 04:53 PM Go to last post
    • Replies: 1
    • Views: 227
    November 10th, 2017, 04:04 AM Go to last post
  3. DE10 pins not found

    Started by D@n, November 3rd, 2017 02:52 PM
    • Replies: 6
    • Views: 374
    November 8th, 2017, 05:01 PM Go to last post
  4. Cyclone V SoC Preloader will not run bare metal app

    Started by jwdonal, September 5th, 2017 01:52 AM
    • Replies: 5
    • Views: 1,303
    November 8th, 2017, 01:53 PM Go to last post
  5. Can't load .jic file to EPCQ device.

    Started by krunal.gandhi, October 25th, 2017 03:15 AM
    • Replies: 2
    • Views: 377
    November 5th, 2017, 08:32 PM Go to last post
  6. sdram addressing troubles

    Started by adrenalin, November 1st, 2017 01:53 AM
    • Replies: 0
    • Views: 252
    November 1st, 2017, 01:53 AM Go to last post
  7. How to set up shared on-chip memory

    Started by sonicsmooth, August 3rd, 2017 10:33 AM
    • Replies: 2
    • Views: 787
    October 27th, 2017, 08:18 AM Go to last post
  8. Can HPS verify FPGA configuration?

    Started by mglapa, October 26th, 2017 05:18 PM
    • Replies: 1
    • Views: 254
    October 27th, 2017, 01:40 AM Go to last post
  9. sending 64 bit from fpga to hs to terminal in pc @10k

    Started by dipin555, October 24th, 2017 04:51 AM
    • Replies: 1
    • Views: 261
    October 27th, 2017, 12:05 AM Go to last post
  10. Loading rbf file on boot from within Linux...

    Started by EauContraire, October 17th, 2017 04:28 AM
    • Replies: 0
    • Views: 348
    October 17th, 2017, 04:28 AM Go to last post
    • Replies: 3
    • Views: 694
    October 16th, 2017, 05:06 AM Go to last post
  11. Cyclone V SoC HPS2FPGA AXI Master - How to enable?

    Started by kstolp, September 12th, 2013 09:41 AM
    • Replies: 5
    • Views: 33,327
    October 15th, 2017, 08:43 PM Go to last post
  12. Cyclone V SoC DK: how to configure awprot/arprot of EMAC?

    Started by Aquu9, October 13th, 2017 08:30 AM
    • Replies: 0
    • Views: 217
    October 13th, 2017, 08:30 AM Go to last post
  13. How to let FPGA get access to HPS pins

    Started by davidc85, March 27th, 2014 05:44 AM
    2 Pages
    1 2
    • Replies: 15
    • Views: 31,728
    September 29th, 2017, 10:16 AM Go to last post
  14. sdram DE0-nano - PLL phase shift

    Started by JeanValjean, September 27th, 2017 01:08 PM
    • Replies: 0
    • Views: 376
    September 27th, 2017, 01:08 PM Go to last post
  15. Does User clock frequency in QSYS for HPS-to-FPGA clock work?

    Started by mawillia, February 26th, 2014 05:31 AM
    • Replies: 2
    • Views: 19,232
    September 25th, 2017, 12:45 AM Go to last post
  16. HPS - FPGA used inside block diagram file.

    Started by ruben.vinuela, March 18th, 2015 10:52 AM
    • Replies: 3
    • Views: 3,554
    September 2nd, 2017, 08:52 AM Go to last post
  17. DE1-SOC power button non-functioning in AS/EPCS mode

    Started by Micks, August 31st, 2017 06:24 AM
    active serial, de1-soc, epcs, power button
    • Replies: 0
    • Views: 532
    August 31st, 2017, 06:24 AM Go to last post
  18. preloader not loading u-boot image

    Started by merciyy, August 17th, 2017 06:43 PM
    baremetal, preloader, sdcard boot
    • Replies: 6
    • Views: 1,520
    August 22nd, 2017, 11:04 AM Go to last post
  19. Post D5M not working with DE1-SoC

    Started by mderryberry, September 16th, 2014 02:30 PM
    d5m, de1-soc, image processing, vga
    • Replies: 5
    • Views: 14,712
    August 16th, 2017, 09:24 PM Go to last post
  20. AXI Problem when simulating Cyclone 5 SOC in Cadence NCSim

    Started by andrewrp, August 11th, 2017 09:16 AM
    • Replies: 0
    • Views: 583
    August 11th, 2017, 09:16 AM Go to last post
  21. Custom Spi Interface controlled by HPS in Arria 10

    Started by Marco Lobba, July 25th, 2017 05:15 AM
    • Replies: 1
    • Views: 762
    August 1st, 2017, 01:46 AM Go to last post
  22. Shared HPS pins pin planning on Arria 10

    Started by Marco Lobba, July 27th, 2017 08:32 AM
    • Replies: 1
    • Views: 702
    July 27th, 2017, 08:31 PM Go to last post
  23. How to work with FPGA-to-HPS bridge

    Started by Sergey, July 24th, 2017 07:06 AM
    • Replies: 0
    • Views: 699
    July 24th, 2017, 07:06 AM Go to last post
  24. FPGA to HPS (AXI Slave) address range issue

    Started by aurash, July 19th, 2017 10:04 AM
    hps
    • Replies: 1
    • Views: 829
    July 19th, 2017, 06:03 PM Go to last post
  25. Seeking HSMC-Transceiver setup assistance for C5G Eval Board

    Started by Scei, July 17th, 2017 09:58 AM
    • Replies: 1
    • Views: 773
    July 19th, 2017, 10:45 AM Go to last post
  26. DE1-SoC problem with tree please HELP!!

    Started by juatafe, July 4th, 2017 02:32 AM
    • Replies: 5
    • Views: 1,785
    July 6th, 2017, 12:51 AM Go to last post
  27. Arria V SOC clock sources

    Started by arria_v_soc_user, August 12th, 2014 04:55 AM
    2 Pages
    1 2
    • Replies: 10
    • Views: 17,315
    July 5th, 2017, 11:14 AM Go to last post
  28. MAC Address changes on reboot

    Started by DaveHorne, January 21st, 2014 08:24 AM
    • Replies: 7
    • Views: 23,672
    June 19th, 2017, 12:23 PM Go to last post

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