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Forum: SoC Discussion

A place to discuss topics related to Altera's SoC products and software for them

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  1. Discussion of all the SoC devices including FPGA and HPS interaction

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    • Threads: 503
    • Posts: 1,909
  2. A discussion on the Linux operating system for SoC devices

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    • Threads: 203
    • Posts: 538
  3. Links and forums for non-Linux operating systems that support Altera's SoC devices.

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    Forum Statistics:

    • Threads: 15
    • Posts: 42
  4. A place to discuss the hardware libraries of the SoC devices. The hardware libraries consist of the SoC abstraction layer and hardware manager.

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    Forum Statistics:

    • Threads: 69
    • Posts: 241
  5. A place to discuss booting SoC devices and the bootloader that makes this happen

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    Forum Statistics:

    • Threads: 77
    • Posts: 315

    Last Post:

  1. Sticky Thread Sticky: Readme!

    Started by BadOmen, January 27th, 2015 11:29 AM
    • Replies: 0
    • Views: 10,162
    January 27th, 2015, 11:29 AM Go to last post
  1. DE1-SoC Interfacing with ADXL345 3 Axis Accelerometer [I2C]

    Started by XXRyanXXL, September 14th, 2017 08:46 AM
    • Replies: 1
    • Views: 148
    Yesterday, 08:13 AM Go to last post
  2. Unhappy YoctoPlugin SoCKit Altera Cyclone 5

    Started by geogrebust, September 22nd, 2016 05:46 AM
    • Replies: 1
    • Views: 938
    September 15th, 2017, 06:47 AM Go to last post
  3. Read DDR to file using HPS2FPGA

    Started by ela05jdc, September 8th, 2017 09:12 AM
    arrow, hps, hps2fpga, soc, sockit
    • Replies: 0
    • Views: 134
    September 8th, 2017, 09:12 AM Go to last post
    • Replies: 1
    • Views: 899
    September 7th, 2017, 12:38 PM Go to last post
    • Replies: 0
    • Views: 203
    September 7th, 2017, 12:24 PM Go to last post
  4. Getting Error with DE0-nano-soc [making u-boot.img]

    Started by jongyun23, August 31st, 2017 10:24 PM
    • Replies: 0
    • Views: 252
    August 31st, 2017, 10:24 PM Go to last post
    • Replies: 0
    • Views: 212
    August 31st, 2017, 10:20 PM Go to last post
  5. Disable FPU on Arria10 SoC FPGA

    Started by karthik.k, August 28th, 2017 11:17 PM
    • Replies: 5
    • Views: 699
    August 30th, 2017, 05:45 PM Go to last post
  6. arria 10 jtag problem while using ds5

    Started by hl8316, August 23rd, 2017 06:30 PM
    • Replies: 2
    • Views: 421
    August 24th, 2017, 06:02 PM Go to last post
  7. Uart Baud Rate Drop

    Started by stefanri, August 17th, 2017 07:09 AM
    • Replies: 4
    • Views: 462
    August 22nd, 2017, 09:32 AM Go to last post
  8. SPI communication

    Started by seongjinkim, August 22nd, 2017 03:42 AM
    • Replies: 0
    • Views: 225
    August 22nd, 2017, 03:42 AM Go to last post
  9. Altera avalon I2C

    Started by kgandhi0408, August 18th, 2017 03:39 AM
    • Replies: 1
    • Views: 342
    August 18th, 2017, 09:03 PM Go to last post
  10. Fixed-link Feature

    Started by MartinFeng_Cytech, August 17th, 2017 12:23 AM
    • Replies: 0
    • Views: 259
    August 17th, 2017, 12:23 AM Go to last post
  11. Qsys Custom component Error

    Started by Marco Lobba, August 8th, 2017 07:29 AM
    • Replies: 2
    • Views: 505
    August 8th, 2017, 10:29 PM Go to last post
  12. Questions about SOC FPGA Preloader and device tree

    Started by OmranAbazid, May 23rd, 2017 02:40 PM
    • Replies: 9
    • Views: 1,821
    August 1st, 2017, 12:28 AM Go to last post
  13. Qsys Custom Peripheral Memory Mapping

    Started by FlipFlop, July 26th, 2017 08:53 PM
    custom peripheral, interrupt, nios, qsys
    • Replies: 2
    • Views: 518
    July 28th, 2017, 12:59 PM Go to last post
  14. Soc simulation in VHDL

    Started by romainht, July 27th, 2017 11:10 PM
    modelsim, vhdl
    • Replies: 2
    • Views: 459
    July 28th, 2017, 01:38 AM Go to last post
  15. Datails about DK-START-5AGXB3N

    Started by Pierre9258, July 26th, 2017 11:25 PM
    • Replies: 3
    • Views: 493
    July 28th, 2017, 01:13 AM Go to last post
  16. About USB memory

    Started by hwada, July 26th, 2017 05:49 PM
    • Replies: 0
    • Views: 355
    July 26th, 2017, 05:49 PM Go to last post
  17. Programming Cyclone V SoC FPGA from or preloader

    Started by Sam16, July 26th, 2017 05:33 AM
    arm, cyclone v, hps, soc
    • Replies: 1
    • Views: 440
    July 26th, 2017, 08:54 AM Go to last post
  18. Cyclone V SOC 256 bit F2S

    Started by shaiko, April 26th, 2017 01:13 PM
    • Replies: 7
    • Views: 2,069
    July 26th, 2017, 08:29 AM Go to last post
  19. Number of FPGA cores used in design

    Started by umutulutas, July 23rd, 2017 10:45 PM
    • Replies: 1
    • Views: 435
    July 24th, 2017, 11:58 AM Go to last post
    • Replies: 9
    • Views: 2,048
    July 20th, 2017, 08:29 AM Go to last post
  20. Getting access to HPS GPIO lines

    Started by rod@ariradesign.com, July 17th, 2017 04:02 PM
    • Replies: 3
    • Views: 579
    July 18th, 2017, 03:32 PM Go to last post
  21. RTL2832U Linux driver compilation on ARM

    Started by kaminari0x01, July 13th, 2017 03:29 PM
    • Replies: 0
    • Views: 380
    July 13th, 2017, 03:29 PM Go to last post
  22. Routing HPS gpio to an LED in FPGA region

    Started by bgh, July 11th, 2017 10:55 PM
    • Replies: 5
    • Views: 721
    July 12th, 2017, 03:59 AM Go to last post
    • Replies: 0
    • Views: 402
    July 11th, 2017, 12:22 PM Go to last post
  23. How to make sure SDRAM write transaction is finished?

    Started by sonycman, July 6th, 2017 01:18 AM
    acknowledge, memory, sdram, write
    • Replies: 0
    • Views: 465
    July 6th, 2017, 01:18 AM Go to last post
  24. DE1-SoC MSEL [00000] or [01110] Unable to program FPGA from HPS

    Started by horia, January 22nd, 2016 11:52 PM
    cyclonev, de1-soc, msel, sockit
    • Replies: 3
    • Views: 2,414
    July 4th, 2017, 01:06 PM Go to last post
  25. terasic / Atlas-SoC Kit and Altera OpenCL compatibility

    Started by ivanfig1, June 24th, 2016 12:54 PM
    atlas-soc, opencl
    • Replies: 6
    • Views: 1,863
    July 3rd, 2017, 03:23 AM Go to last post

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