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Forum: FPGA, Hardcopy, and CPLD Discussion

A place to discuss topics related to Altera's FPGA, CPLD, Hardcopy, and transceiver products (e.g. MAX, Stratix , Cyclone , GX, Hardcopy)

  1. Cyclone V won't configure via active serial

    Started by rod@ariradesign.com, November 13th, 2017 02:14 PM
    • Replies: 9
    • Views: 330
    Yesterday, 02:21 PM Go to last post
    • Replies: 8
    • Views: 210
    Yesterday, 12:21 PM Go to last post
  2. Would you recommend "new" Cyclone 10 GX now for a new design??

    Started by FateS, November 16th, 2017 08:38 AM
    • Replies: 2
    • Views: 125
    Yesterday, 09:00 AM Go to last post
  3. DDR II SDRAM Data Mask Pins assignments

    Started by mohsin_qau, November 9th, 2017 05:15 AM
    • Replies: 2
    • Views: 240
    Yesterday, 01:27 AM Go to last post
  4. MAX10 PLL Not Locking - KHz instead of MHz

    Started by wblee, Yesterday 12:54 AM
    • Replies: 0
    • Views: 72
    Yesterday, 12:54 AM Go to last post
  5. Unhappy Can't fit fan-out of node into a single clock region

    Started by tiabph, September 4th, 2009 04:46 AM
    • Replies: 2
    • Views: 45,862
    November 16th, 2017, 02:42 AM Go to last post
  6. MAX10 constraining IO problems

    Started by cmorley, November 15th, 2017 07:45 AM
    • Replies: 1
    • Views: 125
    November 15th, 2017, 01:05 PM Go to last post
  7. problem with adaptive FIR ,i realy need your help

    Started by boyzzun, March 3rd, 2014 07:44 AM
    • Replies: 9
    • Views: 19,234
    November 15th, 2017, 12:16 PM Go to last post
  8. Stuck on Fast QSPI

    Started by skrasms, November 7th, 2017 10:47 PM
    • Replies: 7
    • Views: 476
    November 15th, 2017, 01:49 AM Go to last post
  9. interfacing to epcq from fpga?

    Started by alexander14, November 7th, 2017 12:13 PM
    • Replies: 2
    • Views: 247
    November 14th, 2017, 08:29 AM Go to last post
  10. MAX 10 and the STAPL byte-code player

    Started by LordNikon, March 2nd, 2017 05:27 AM
    • Replies: 5
    • Views: 1,109
    November 14th, 2017, 04:53 AM Go to last post
  11. Cyclone V Hard Memory Controller MPFE bandwidth

    Started by simonkbrown, November 13th, 2017 04:45 PM
    cyclone, ddr, hmc, mpfe
    • Replies: 0
    • Views: 102
    November 13th, 2017, 04:45 PM Go to last post
  12. MAX10 PLL External Clock Output

    Started by JDL, November 7th, 2017 08:34 AM
    pll max10
    • Replies: 2
    • Views: 252
    November 13th, 2017, 03:55 AM Go to last post
    • Replies: 5
    • Views: 349
    November 13th, 2017, 01:46 AM Go to last post
  13. Product Key MAX 7000

    Started by MarcFigliuolo, November 10th, 2017 07:09 AM
    • Replies: 2
    • Views: 243
    November 12th, 2017, 07:15 PM Go to last post
  14. M20K block related build error

    Started by matttsai, November 4th, 2017 06:05 AM
    • Replies: 2
    • Views: 330
    November 12th, 2017, 07:05 PM Go to last post
  15. MAX 10 10M25SAE144 problem boot from internal flash

    Started by siliconvalley, November 5th, 2017 09:27 AM
    config, max10
    • Replies: 7
    • Views: 455
    November 10th, 2017, 05:34 PM Go to last post
  16. Problem with simulation and implementation of code in DE0 Nano Cyclone IV kit

    Started by abenitez, November 7th, 2017 08:21 AM
    2 Pages
    1 2
    • Replies: 10
    • Views: 525
    November 10th, 2017, 11:16 AM Go to last post
  17. MAX10 RAM (M9K) content at power up?

    Started by arg, November 9th, 2017 01:09 PM
    • Replies: 2
    • Views: 256
    November 10th, 2017, 02:01 AM Go to last post
  18. Config Flash EPCQ4A Cylone II

    Started by MarcFigliuolo, November 6th, 2017 02:56 AM
    • Replies: 3
    • Views: 305
    November 9th, 2017, 10:52 AM Go to last post
  19. Cyclone IV GX DDR

    Started by Brick, March 15th, 2017 08:56 AM
    cyclone iv-e, cyclone iv-gx, ddr
    • Replies: 4
    • Views: 1,480
    November 8th, 2017, 06:33 AM Go to last post
  20. DE0-CV board control panel

    Started by mmostafa, October 4th, 2017 07:51 AM
    • Replies: 1
    • Views: 453
    November 8th, 2017, 04:00 AM Go to last post
  21. Arria 10 IOPLL output not synchronous with input

    Started by mikezgrtf, November 6th, 2017 01:25 PM
    • Replies: 5
    • Views: 294
    November 8th, 2017, 12:22 AM Go to last post
    • Replies: 4
    • Views: 395
    November 7th, 2017, 11:47 AM Go to last post
    • Replies: 3
    • Views: 261
    November 7th, 2017, 10:58 AM Go to last post
  22. MAX10 10M50SCE144C8G trouble on programming

    Started by rromano001, February 5th, 2017 02:03 PM
    • Replies: 9
    • Views: 1,591
    November 6th, 2017, 12:33 PM Go to last post
  23. Cyclone V DDR3 package deskew

    Started by amesser, November 4th, 2017 12:00 PM
    • Replies: 1
    • Views: 287
    November 6th, 2017, 12:08 AM Go to last post
  24. Question MAX V CPLD Reset and OE

    Started by handaxiao, October 30th, 2017 03:16 PM
    • Replies: 8
    • Views: 642
    November 5th, 2017, 03:40 AM Go to last post
  25. Disable Device ID check during JTAG Programming

    Started by edgar85, October 30th, 2017 06:42 AM
    2 Pages
    1 2
    • Replies: 10
    • Views: 840
    November 4th, 2017, 11:23 AM Go to last post
  26. Unhappy MAX10 UFM writing takes much longer than expected

    Started by andi6510, October 27th, 2017 08:24 AM
    max10, ufm
    • Replies: 7
    • Views: 805
    November 3rd, 2017, 10:29 AM Go to last post

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