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  1. SoC FPGA Virtual Target
  2. ARM DS-5 device_browser.py failed
  3. How can I get data from FPGA frabic via FPGA-to-HPS?
  4. Cyclone V FPGA to HPS at high frequencies
  5. Timing delay of reading from second RAM in FPGA.
  6. TRACE Debug on Cyclone V HPS - has anyone used DSTREAM
  7. DTB (Device Tree Blob Files) Step by Step Guide DE1-SoC ** HELP ! ** GPIO Q14.0
  8. Data Transfer from FPGA to HPS Via FPGA connected SDRAM (DE1-SoC)
  9. uclinux on nios
  10. SoCKit pin assignment
  11. The software build error about onchip_ram overflowed
  12. Why qsys reports address overlap error?
  13. Terasic ETHERNET-HSMC Card and Arrow SoCkit
  14. Why qsys doesn't report error when Avalon-MM data width mismatch?
  15. ddr3 sdram controller (UniPHY) afi_half_clk doesn't work but status signals work fine
  16. How to update the existing BSP after I update the FPGA design?
  17. OpenCore Plus Time-limited File and Linux Worklflow
  18. FPGA-HPS Bridge correct bringup and JTAG lockups
  19. Why none getchar(), getc, fgetc() work ?
  20. If I want to put software program elf file into flash, do I need a flash controller?
  21. sources for JtagClock or how to set default jtag clock
  22. Preloader execution issues / Arrow SoCkit board
  23. Boot HPS part from FPGA
  24. Boot HPS from FPGA doesn't work
  25. eMMC OS bring-up: Best method to write SoC HPS image to embedded MMC memory
  26. Baremetal programming with Arrow Cyclone V SoCKit
  27. Baremetal LCD programming with Arrow Cyclone V SoCKit
  28. Cyclone V SoC - Time execution function - Cycle count
  29. 5CSXFC6D6F31- Altera Cyclone V SoC Dev Env
  30. Readme!
  31. Nios BSP debug
  32. Problem Hooking a USB to Serial Adapter to Cyclone V on the go USB
  33. HPS-FPGA data transfer and DMA slow control problem
  34. CycloneV Loaned Pin's Open-Drain configuration
  35. Video-in port in DE1-SoC Computer System availability
  36. How to transplant vlc player on the nios ?
  37. Enpiron power Device(EN6337QI & EN6347QI)
  38. Programming emmc Flash using JTAG!
  39. problem trying to run Board Test System on windows 8
  40. Arrow Cyclone V Sockit I/O configuration
  41. DS-5, how can i make launching the debugger from the command-line console
  42. DDR3 without leveling clock length
  43. Altera cyclone5 board can't start without serial cable plugged
  44. Vector sizes for Qsys generated HPS memory pins
  45. What's the difference between an Avalon MM Master and an Avalon MM Slave
  46. Is access to memory Atomic ?
  47. boot from S25FL512S
  48. Does EDS 13.1 deferent with EDS14.1?
  49. Fpga2Hps Bridge
  50. Altera SOC Developers Forum
  51. Choosing an RTOS for the Cyclone V ARM Processor
  52. Partial Reconfiguration Cyclone V SoC Development Kit (DK-DEV-5CSXC6N)
  53. How to visit HPS2FPGA in linux for cyclone V(DE1-SoC)?
  54. Help in DS-5 debug script to load bare metal application into SDRAM address 0
  55. Support and maintenance for DS-5 Community Edition expired on lug 31, 2015
  56. Where to connect custom Avalon-MM Slave avalon_slave bus in Qsys?
  57. ERROR: tb.dut.master_0.mm_master_vhdl_wrapper.<protected> .<protected>: Illegal c
  58. How to get bare metal app running independently on SoCkit?
  59. FPGA-SoC on Arrow SoCKit (Fitter error)
  60. Cyclone V SOC PCI Express access on both NIOS and ARM at same time
  61. How to handle SCU at runtime on Cortex-A9
  62. Arrow Cyclone V SoCKit Hard DDR3 Memory controller interface
  63. EN5329QI efficiency vs Iout experiment
  64. Cyclone V transceiver LVDS reception problem
  65. Best way to share DDR w/ FPGA
  66. SOPC Make Script and bsp-editor
  67. Golden Design Guidance
  68. reset manager status register values after power up
  69. Cyclone V HPS canít read RS232 data
  70. HPS DDR memory access for Preloader and UBoot
  71. where can i get a SGMII design example for reference?
  72. teraterm setting for sd card boot up. in cyclone 5
  73. hps to fgpa or fpga to hps example use case
  74. Replace the GHRD SD MMC to be a smaller EMMC chip?
  75. Using ADC with HPS on DE1-SoC Board
  76. FPGA manager core in hps
  77. Address Space in HPS
  78. CycloneVRGMIIExampleDesign not working
  79. Connecting 2nd Jtag2AVM to f2h_axi_slave causes system console to hang up
  80. Communication stop's (ping) after Running DS-5 Debug
  81. Memory Controller of the Socrates || Cyclone V SoC
  82. Double Tap DE0-Nano-SoC G-Sensor
  83. SDRAM DDR2 support in Cyclone soc memory controller
  84. Axi lite device tree support for usage
  85. Interrupt setting procedure. in arm SoC.
  86. [U-boot] i2c probe -> no valid chip addresses
  87. HPS ENET (EMAC) MAC Address failed to set
  88. No licenses 'RSTM_Pool_Pro' available
  89. Saving a project to on board flash memory to boot on start up
  90. bsp compilation error. #scrubbing should be enabled!
  91. [GHRD] EMAC1 in Peripheral Mux
  92. [ArriaV EVB] ENET_HPS_INTN [EMAC1]
  93. MAC address in HPS -> could be set any?
  94. Use SDRAM simultaneously with HSP and FPGA
  95. DDR3 freq report
  96. DDR3 Output Drivers Termination/Impedance
  97. UART (RS-232 Serial Port) IP usage
  98. NIOS processor integration
  99. Uart ip
  100. Arria 10 u-boot generation error, incomplete
  101. UART RS-232 IP -> simulation
  102. soc release notes
  103. SWAP EMAC TX RX bits ( MAC <-> PHY )
  104. Reconfigure FPGA from USB-Blaster on a running HPS system
  105. Making Qsys Master Component
  106. Debugging of the FPGA portion using the HPS ARMs & Linux
  107. about NIOS II programme download problem
  108. AXI3 Lightweight Bridge
  109. Cannot add bi-directional pins to SignalTap-II... Should it be so?
  110. DE1-SoC MSEL [00000] or [01110] Unable to program FPGA from HPS
  111. Avalon Interface -> burst transaction
  112. Custom Instructions on HPS
  113. How to implement an NoC (Network on Chip) in my DE1-SOC (Nios-II, Qsys)?
  114. Cyclone V 5CSEBA2 Thermal Configuration
  115. Four video moudules' streams + wifi
  116. EDS QSPI programming problem
  117. SOC CyV ARM and ethernet connection
  118. Cyclone V SX SoC Development Board serial for HPS
  119. Simple tutorial for bare metal programming
  120. Question on Arria NAND flash compatibility on page and block sizes
  121. What is the function of hps_reset?
  122. modifying ghrd_top.v
  123. Is there any example including "connecting custom ip to avalon bus "?
  124. Cyclone V socfpga issues
  125. EMAC interface RGMII1 HPS on LINUX
  126. Cyclone V SoC / Boot from QSPI issue with Quartus 15.0 and Angstrom distribution
  127. QSPI booting problem
  128. How do I will solidify the nios ii program in fpga
  129. HPS Timing Warnings
  130. My AXI4 Lite slave hangs CPU after read. Write transactions work correctly
  131. Where is PCIeRootPortWithMSI DMA transfer test source code (dmaxfer.c) located?
  132. Use SDRAM from SoC and VHDL component
  133. DMA vs MSGDMA
  134. DMA read timeout while using PL330?
  135. Damn fpga2sdram inerface!
  136. How to build Linux/Nios2 kernel with MMU on the Arria10 GX FPGA development board ??!
  137. De1-SoC Linux Ubuntu Desktop - quartus project
  138. Error: (vsim-3828) Could not link vsim_auto_compile.dll
  139. Change buswidth on the hps2fpga bridge
  140. DE1-SoC Board Connector Mate Question
  141. terasic / Atlas-SoC Kit and Altera OpenCL compatibility
  142. Altera lab SoC FPGA Linux training
  143. External memory (A2V64S40CTP, IS61WV25616BLL, S29AL032D70TFIO4)
  144. FreeRTOS
  145. How to transfer data from FPGA to HPS and vice-versa in Cyclone V
  146. accelerate cyclone V
  147. ESOC Board Fatal Error
  148. Controlling HPS pins from FPGA using Cyclone 5
  149. FPGA to HPS SGDMA data transfer
  150. using UART in DE1-SoC board
  151. Using HPS in Quartus 15.0 generates false output
  152. OS on Cyclone 5 HPS without hard memory controller
  153. Is Altera a Leader in SoC?
  154. DE1-SOC SD card file system
  155. Linux PTP IEEE 1588
  156. [HELP] DE1 SoC - ADC Controller
  157. Need to Flush L2 cache on Cyclone V even though disabled ?
  158. Is it possible to receive runt ethernet packets with Cyclone V HPS MACs ?
  159. Arria 10 External Memory Interface Pin Infromation
  160. H264 software decoder
  161. Use Monitor Program compiler Cortex- A9 program, prompt math library error
  162. Cyclone 5 pcie example project failure
  163. Cyclone 5 PLLs
  164. Custom CycloneV Board based on DE1-SOC, USB3300 issue.
  165. YoctoPlugin SoCKit Altera Cyclone 5
  166. Interrupts using the ARM core and the GIC
  167. Help using ACP Port with EMAC on Cyclone V
  168. Cyclone 5 PLLs part II
  169. Cyclone V HPS eMMC Physical Interface
  170. Changing HPS SDRAM parameters in Qsys need to rebuild the whole FPGA
  171. Reuse values of Qsys generics in C++ app
  172. Cyclone v HPS SDRAM PLL source
  173. Impossible to do ECO on DE1-SoC (Cyclone V)
  174. Check FPGA / bridges before accessing them
  175. Resizing Linux image for 200GB SD card
  176. newbie to SOCkit
  177. How to access memory with Custom IP?
  178. Running a C code without uploading Linux to DE1-SoC
  179. make_sdimage.py creates invalid ext3 partition
  180. HPS GPIO's ouputs stuck in high impedence?
  181. Does HPS I2C peripheral support clock stretching?
  182. ArriaV SoC : DDR ECC Error
  183. Run Python on Cyclone V SoC
  184. Custom accelerator circuit design with DMA
  185. Arria10 - Send linux command to the CPU through UART without minicom ?
  186. Msgdma csr status - Altera SoC Workshop Series - Lab 4: Linux FFT Application
  187. HPS to FPGA AXI LITE clock crossing brige timeout
  188. From PIO IP to HPS SDRAM (Cyclone V SE)
  189. Can .RBF Raw Binary be run natively from power on from SPI flash?
  190. HPS side connected to mailbox
  191. Understanding Inter-Processor Communication with Mailbox HW via mmap
  192. Quartus II 13.1 Programmer Hardware Setup
  193. QuadSPI interface initialization
  194. access to FPGA registers using ARM
  195. Basic interrupt example not working due to Nios crash during startup code.
  196. mSGDMA ST-MM to SDRAM - Issue
  197. vsim-3827 error running load_sim.tcl for Cyclone V Soc design
  198. Cyclone V SOC ARM DMA
  199. Arria 10 Ethernet Connection Issue
  200. Ethernet to UART Converter NIOS - HAL or MicroC?
  201. Using FPGA to HPS-Bridge
  202. Arria 10 with separate hardened DDR controller for PL and HPS
  203. "Taking the SDRAM bridge out of reset"
  204. Building a custom kernel for the DE1-SoC...
  205. Can I connect USB to logic part on Altera SoC's
  206. HPS load hangs after RBF is loaded
  207. Looking for HPS to FPGA custom component integrations guideline using Qsys
  208. GPIO access using Qsys tool and Linux in deo nano
  209. Read out uninitialized SRAM m10K from FPGA fabric on Cyclone V SoC
  210. Unable to read/write data on h2f_axi_master port
  211. Beginner question regarding HPS, Qsys and NIOSII
  212. How to sned more than 32bits of data to HPS form FPGA custom ip
  213. how to link the file to the SDRAM in qsys tools
  214. got this error when using eclipse
  215. Cyclone V SOC 256 bit F2S
  216. the statement in console tab
  217. Interrupt handling problem using linux with DE1_SoC cyclone V
  218. can't generate nios II .sof file
  219. F2H_SDRAM "WAITREQUEST" doesn't return to '0'
  220. Help! My Kernal is Panic and He Is Trying to Kill Someone!!
  221. sharing of local_memory between Work Items on SoC FPGA (Cyclone V)
  222. Ethernet data stream from HPS On-Chip RAM
  223. "Unknown Device" (DE0-nano) No USB connection
  224. Hard Processor System's AXI SDRAM
  225. Questions about SOC FPGA Preloader and device tree
  226. .rbf image compatability
  227. SoC FPGA Ethernet Performance
  228. How to include math library?
  229. DE0-Nano-SoC, Strange error reading SD/MMC
  230. HPS Peripheral pins assignment.
  231. Nios II/f and DDR4 memory with Arria 10 dev board
  232. Cyclone V sdcard pull-up
  233. Clock issue with simple DDR4 implementation for Arria 10 SoC Dev Kit
  234. quartus ii 17.0 download firmware failed
  235. Trouble with setting up Ethernet
  236. Learning Linux and choosing best Linux for Altera Arria V SoC Kit
  237. Using the VGA-Adapter with Terasic DE1-SoC
  238. How to make sure SDRAM write transaction is finished?
  239. Writing to Avalon Memory-Mapped On-chip RAM from Avalon Streaming
  240. Routing HPS gpio to an LED in FPGA region
  241. RTL2832U Linux driver compilation on ARM
  242. Getting access to HPS GPIO lines
  243. Number of FPGA cores used in design
  244. Programming Cyclone V SoC FPGA from or preloader
  245. About USB memory
  246. Qsys Custom Peripheral Memory Mapping
  247. Datails about DK-START-5AGXB3N
  248. Soc simulation in VHDL
  249. Qsys Custom component Error
  250. Fixed-link Feature