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Thread: System Verilog Pin Assignment Issues

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    Default System Verilog Pin Assignment Issues

    Newbie question - Just bought my first FPGA and working through examples to understand design and coding. My first example using a block diagram and .v file worked fine. My next try was using a book that has System Verilog examples. When entering System Verilog coding and going to Pin Planner in Quartus Prime 18 (Lite Edition), the pin definitions are not the same and not correct. Any idea what I am doing wrong? Same device number was used.

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    Default Re: System Verilog Pin Assignment Issues

    Not sure I understand the question. You select pin location assignments yourself. The code has nothing to do with it (unless you put pin assignments directly in your code using attributes). Can you explain a little more about what is going on?

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    Default Re: System Verilog Pin Assignment Issues

    Quote Originally Posted by sstrell View Post
    Not sure I understand the question. You select pin location assignments yourself. The code has nothing to do with it (unless you put pin assignments directly in your code using attributes). Can you explain a little more about what is going on?
    I think I figured out the problem, but not a solution. I'm using a project for another board that has 3 buttons. I only have two, but I have 4 slide switches. I planned to use one of the slide switches for my input for the missing button. Problem seems to be the manual gives me the location for SW0 as Y24, which I set up in my pin planner. However, I now realize pin Y24 is for a clock output. Explains why my design is not working. So, I'm not sure which pin is the correct one for SW0. I downloaded the pin file for my fpga from Intel, but it is Greek to me. They list 5 MSEL locations (hoping), but it will not let me use that pin. I have a Cyclone V, 5CSEBA6U23I7NDK. I attached 2 png files to show how I cam to my conclusion.
    Attached Images Attached Images

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    Default Re: System Verilog Pin Assignment Issues

    The second picture looks like the manual for a particular development kit. Unless you are using that kit, pin locations need to be manually assigned to match how they are connected on your board. Pins like the MSEL pins are fixed hardware pins with fixed functions. They are not general purpose I/O (GPIO) (though some fixed hardware pins on some devices can be used as GPIO after device programming).

    Which dev kit are you using?

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    Default Re: System Verilog Pin Assignment Issues

    Terasic de10-nano. Thanks for you assistance and patience!

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