Altera Forums - FPGA, Hardcopy, and CPLD Discussion

Please help me to identify device.

waveform — Fri, 10 Sep 2010 12:44:13 GMT

We got our newly designed instrument with altera device istalled on it: Stratix III EP3SL50F780C2N. See this picture:

I turn this device on and read with JTAG device code. See next picture:

Here is two unconformities:
1) Device marked as "Startix(tm)", although it must be marked as "Stratix(tm) III".
2) JTAG reads code EP3SE50, although device is marked as EP3SL50.

Please, help me to identify, is it a native altera manufactered device or it may be a re-marked or tampered with to represent a different device or counterfeit?

legacy support freeze PCIe

ARTEM_BOND — Thu, 09 Sep 2010 14:21:34 GMT

I'm try to implement legacy interrupt support in Arria 2 GX. MSI-X working good. But when I try to generate legacy interrupt it's freeze whole PC.

I'm use only two signals from PCIe core. Input is app_int_ack and output app_int_sts. When I need a make interrupt I'm set app_int_sts to 1 and wait for app_int_ack became to 1. After I'm set app_int_sts to 0. But It's don't work.

Attached Images

legacy.gif (1.3 KB)

Terasic Byteblaster

ajaymn — Thu, 09 Sep 2010 10:51:06 GMT

Hello
I am using a Terasic USB Byteblaster. I see that the Pin # 1 (DCLK - DCLK) and Pin # 9 (ASDO -> ASDI) of the Byteblaster are shorted. Should they be shorted by default or would they have been shorted during the development process ? I did not see my current increase when I was bringing up the board / trying to program the Cyclone III (EQFP package) or did not hear a pop or anything suspicious that could have shorted the two pins.

I found that out when I was checking the connections to ensure that I had the connections for the AS mode correctly done. I saw the short when the ByteBlaster was connected on the board and it was gone after I removed the Byteblaster. Thats how I found out about the short.

I am programming in AS Mode and Quartus II says "Can't recognize silicon id for Device 1"

Any help will be appreciated.

Thanks
Ajay

High speed DAC/ADC for Dev Kits?

mwieckow@gmail.com — Thu, 09 Sep 2010 10:34:48 GMT

Hey,

I am planning to buy a Stratix IV Dev Kit for my research project. I have found that there are 150/250 MSample/s ADC/DAC cards connected through this HSMC. The thing is I would require higher rates (1GS/s on both DAC and ADC). Where can I find compatibile cards?

BTW, there is no product inquiry contact form on Altera's website, what's with that?

Kind regards,
Marcin.

USB Blaster DE2

teus.fon — Wed, 08 Sep 2010 23:08:19 GMT

Hello, Now I have one more question, I wanna know about the usb blaster, i will buy DE2, then i wanna know if usb blaster will come with the board, or i need to buy separate.

So, if usb blaster doesn't come with the board, i need to buy, or i can program the fpga with usb port.

Thanks for all :cool:

Difference: Quartus Web Edition 9.2 and Quartus Subscription 9.2

teus.fon — Wed, 08 Sep 2010 13:58:11 GMT

Hello, I am using the Quartus Web Edition 9.2, and i wanna start to use Quartus Subscription 9.2 . I know this software is paid, then i wanna know the difference between both. Cause if is the same thing i will continue usando Quartus Web Edition. Could somebody explain, or pass some site than i can read about?

thanks

Got Confdone signal but ist not working right

Woody Allen — Wed, 08 Sep 2010 09:38:02 GMT

Hi, i'm news to this forum and already have a problem. (Most of the user joined this forum this way i guess).

I'm using

- Cyclone 3 EP3C10F256C8
- Quartus 2 V8.0
- Byteblaster 2

I whant to run a simple test program to start. If i mean simple, i mean:

begin
clk0 <= '0';
clk1 <= '0';
clk2 <= '0';
clk3 <= '0';
clk4 <= '0';

end;

Everything seems alright, quartus 2 gives warnigs but not extrodinary. The programmer (JTAG) detects 2 devices

EP3C10/5
UNKNOWN_792603F

The second device is a processor (i know cause its the same numbers)
The first is the FPGA the device. Now the device he detects is not the same as EP3C10F256C8, is it? Quartus gives programming succesfull and CONF_DONE pin goes HIGH but the INIT_DONE stays low. What can be the problem?

Thanks anyway for the responds that will follow.

Anyone can run DDR2 stably with Stratix IV?

Nickqian — Wed, 08 Sep 2010 07:48:02 GMT

Anyone can run DDR2 stably with Stratix IV and Quartus 9.1 Sp2 or above?
I've tried about 8 board(the same PCB layout) which has 1 Stratix IV 530 ES device and 7 Stratix IV 530 FPGA. The board with ES chip can run stably, other boards run unstably.

0) All calibrations are OK. can read and write data. But it's unstable.
1) Reset 10 times, PNF will fail in a few seconds for about 2 or 3 times. Other resets can run about ten or twenty minutes.
2) I only use the generated "high performance controller(it uses Altmemphy, not UniPHY)" and the driver and the example top. No other design.
3) It runs at about 166MHz at PHY side. 333MHz or 266MHz have the same result. So I don't think it's the problem of PCB layout.
4) I've used the "debug-toolkit.zip" to debug. It's weird that all 4 DQS group(32-bit) looks good enough. But the "interface level" result is BAD. The center sample point is near to the left invalid step. I almost thought that this can directly cause the instable DDR2 operation. A picture has been attached.

Thanks a lot for all your opinions!!

Attached Images

IRAM.JPG (123.8 KB)

PLL connections to SERDES in StratixIV

paulte — Wed, 08 Sep 2010 07:30:51 GMT

Hi,
I'm trying to determine whether the serializers and deserializers for a Stratix IV GX can be driven from the same PLL, but with different phases of the VCO, without using the DPA circuits.
I am receiving and transmitting parallel data (at 1Gbit/sec) from external devices that use a common clock, but there is skew between the different devices data busses (but not within the bus). Thus I need to drive the SERDES to match the external devices setup and hold times, and that requires that I use different PLL outputs (c0, c1 etc) to drive the SERDES, and other divided outputs (c2, c3 etc) for the word size registers.
The device handbook implies I can do it, but I haven't had a successful compile yet. This is of course all happening against a background of malfunctioning ALTLVDS_TX and ALTLVDS_RX MegaWizards and (just now) the fitter crashing out.
Any comments welcome! I'm using 10.0 SP1.

NiosII IDE 中alt_timestamp()函数测量时间的精度是多少

gongyue1000 — Wed, 08 Sep 2010 05:27:12 GMT

哪位朋友能说一下，NiosII IDE 中alt_timestamp()函数测量时间的精度是多少？
main()函数中设置时间点部分如下：
void main ()
{
alt_u32 time1;
alt_u32 time2;
alt_timestamp_start() ; //开启时间标记服务
time1 = alt_timestamp(); //测量时间点1
usleep(100);
time2 = alt_timestamp(); //测量时间点2

return 0;
}

问题是：如果测usleep(1000)，则测量误差不大。但如果测usleep(1)，则显示运行此函数用22us，不是1us；如果测usleep(2)，则显示运行此函数用20us，不是2us；如果测us leep(10)，则显示运行此函数用27us，不是10us；

为什么？是 alt_timestamp()测时间不准，还是usleep(1)延时本身就不是1us？

EP2C20F484C7 and EP2C35F672C6

teus.fon — Wed, 08 Sep 2010 01:41:48 GMT

Hello, I will buy DE2 or DE1, but i wanna know what is the difference about FPGA of Cyclone II EP2C20F484C7 and EP2C35F672C6, could you explain for me?

Thanks

FPGA with TTL outputs

engineer86 — Tue, 07 Sep 2010 13:23:15 GMT

I am in need of an FPGA or CPLD device with TTL outputs. If there is not such a device available, does anyone have any recommendations for a voltage translator of some kind or another device that will fit my need? Thanks!

using memory Bits

catmoe88 — Tue, 07 Sep 2010 12:19:58 GMT

Hi i wrote a vhdl design in which i wanted to buffer data like this:
WHEN 0 => ausgangimag0 <=ausgangimag0 + resultim;ausgang2 <= ausgangimag0;
WHEN 1 => ausgangimag1 <=ausgangimag1 + resultim;ausgang2 <= ausgangimag1;
WHEN 2 => ausgangimag2 <=ausgangimag2 + resultim;ausgang2 <= ausgangimag2;
WHEN 3 => ausgangimag3 <=ausgangimag3 + resultim;ausgang2 <= ausgangimag3;
WHEN 4 => ausgangimag4 <=ausgangimag4 + resultim;ausgang2 <= ausgangimag4; .... and so on
only much more. when i compile the design i get the error: "Error: Design contains 77634 blocks of type combinational node. However, device contains only 33216." But the memory Bits of the FPGA are empty (0 / 483840). How can i use them to buffer the data?

Why Cyclone III cost as much power as Cyclone II?

zrx737 — Tue, 07 Sep 2010 02:37:54 GMT

I believe 65nm process technology can help to lower power consumption than 90nm.
However the POWERPLAY and board test result did not agree with that.
I have a design for data transceiving using RS485.The FPGA is in charge of 8B/10B,CRC,RS. Nios core is used.
I change the project from CycloneII to Cyclone III,simulate the two project with powerplay using vcd files.The result showed the power comsumption are nearly the same.
I have two PCB board with same design and different FPGAs,EP2C35 and EP3C40.The EP3C40 board comsumes a little more power than EP2c35 did. And the 2.5V power comsums 50-80mw,while EP2c35 do not have a 2.5v comsumption.
This confuse me a lot . I use quartus 8.1. 50% logic.

Flash generated using sof2flash fails to configure fpga

dipen — Mon, 06 Sep 2010 11:35:13 GMT

Hi ,
I have Stratix IV development kit ,
I want to load Flash file converted using sof2flash utility.
when i use nios2-flash-programmer it works fine .
but it fails to configure FPGA from flash when i cycle power the board .

Anybody have idea ?

nios2-flash-programmer failed!

lameck — Mon, 06 Sep 2010 10:40:21 GMT

I Desgin a new EP2C8 board with 8MByte flash(S29Gl064N), but it can not download file with nios2-flash-programmer. please help me!!!

it can run Memory Test example and it's OK!

but only nios2-flash-programmer failed!!!

this is output messages:
1. Memory Test
----------------------------------
Memory Test Main Menu
----------------------------------
a: Test RAM
b: Test Flash
e: FlashErase
m: TestFlash(SHOWMAP, CFI)
q: Exit
----------------------------------
Select Choice (a-b): [Followed by ]b
Enter the name of the CFI flash device to be opened,
or just press to open "/dev/ext_flash"
>/dev/cfi_flash
-Successfully opened /dev/cfi_flash
-Region 0 contains 8 blocks.
-Checking Region 0 for erased blocks.
-Block 1, at address 0x2000 identified.
-Would you like to test this block? (y/n)y
-Starting Flash Test.
-Testing "alt_write_flash" and "alt_read_flash".
pass 1 - passed.
pass 2 - passed.
-Testing "alt_erase_flash_block". passed.
-Testing "alt_write_flash_block". passed.
-Testing unaligned writes. passed.
-Returning block 1 to its erased state.
-Flash tests complete.
-Closing flash device "/dev/cfi_flash".
Press enter to continue...

2. nios2-flash-programmer:
# Programming flash with the datafile
"$SOPC_KIT_NIOS2/bin/nios2-flash-programmer" --base=0x00000000 --cable='USB-Blas
ter [USB-0]' --sidp=0x00802010 --id=1524664086 --timestamp=1283755809 --instance
=0 "bit8.flash"
Using cable "USB-Blaster [USB-0]", device 1, instance 0x00
Resetting and pausing target processor: OK
Reading System ID at address 0x00802010: verified
: Checksumming existing contents
00000000 : Reading existing contents
00008000 : Reading existing contents
Checksums took 0.3s
00000000 ( 0%): Erasing
00008000 (50%): Erasing
Erased 16kB in 0.1s
00000000 ( 0%): Programming
Program failed
Leaving target processor paused

please help me!!!

Help!!! cfi flash programmer error

lameck — Mon, 06 Sep 2010 01:45:01 GMT

I use nios2-flash-programmer command with argument "--debug" , it shows:
Using cable "USB-Blaster [USB-0]", device 1, instance 0x00
Resetting and pausing target processor: OK
Reading System ID at address 0x00802010: verified
Found CFI table in 16 bit mode
Raw CFI query table read from device:
0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
20: 51 00 52 00 59 00 02 00 00 00 40 00 00 00 00 00 Q.R.Y.....@.....
30: 00 00 00 00 00 00 27 00 36 00 00 00 00 00 07 00 ......'.6.......
40: 07 00 0A 00 00 00 03 00 05 00 04 00 00 00 17 00 ................
CFI query table read from device:
10: 51 52 59 02 00 40 00 00 00 00 00 27 36 00 00 07 QRY..@.....'6...
20: 07 0A 00 03 05 04 00 17 02 00 05 00 02 07 00 20 ...............
30: 00 7E 00 00 01 00 00 00 00 00 00 00 00 00 00 00 .~..............
CFI extended table read from device:
0: 50 52 49 31 33 10 02 01 00 08 00 00 02 B5 C5 02 PRI13...........
10: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
Read autoselect code 0001-007E (in 16 bit mode)
No CFI override data for [FLASH-0001-007E]
Device size is 8MByte
Erase regions are:
offset 0: 8 x 8K
offset 10000: 127 x 64K
Device supports AMD style programming algorithm
Multi-byte programming with 32 byte buffer
Sector erase timeout is 16s
Word program timeout is 1ms
Buffer program timeout is 4ms
: Checksumming existing contents
00000000 : Checksum failed - needs erase then program
00002000 : Checksum failed - needs program
00004000 : Checksum failed - needs program
00006000 : Checksum failed - needs program
00008000 : Checksum failed - needs program
0000A000 : Checksum failed - needs program
0000C000 : Checksum failed - needs program
0000E000 : Checksum failed - needs program
00010000 : Checksum failed - needs program
00000000 : Reading existing contents
Checksums took 0.0s
00000000 ( 0%): Erasing
Erased 8kB in 0.0s
00000000 ( 0%): Programming
Program failed
Leaving target processor paused

and i make a override file "ovet.txt" like this:
[FLASH-0001-007E]
CFI[0x10] = 0x51
CFI[0x11] = 0x52
CFI[0x12] = 0x59
CFI[0x13] = 0x02 # The primary command set, found at CFI table -
CFI[0x14] = 0x00 # addresses 0x13 and 0x14 is overridden to 0x02, 0x00.
CFI[0x15] = 0x04
CFI[0x16] = 0x00
CFI[0x17] = 0x00
CFI[0x18] = 0x00
CFI[0x19] = 0x00
CFI[0x1A] = 0x00
CFI[0x1B] = 0x27
CFI[0x1C] = 0x36
CFI[0x1D] = 0x00
CFI[0x1E] = 0x00
CFI[0x1F] = 0x07
CFI[0x20] = 0x07
CFI[0x21] = 0x0A
CFI[0x22] = 0x00
CFI[0x23] = 0x03
CFI[0x24] = 0x05
CFI[0x25] = 0x04
CFI[0x26] = 0x00
CFI[0x27] = 0x17
CFI[0x28] = 0x01
CFI[0x29] = 0x00
CFI[0x2A] = 0x00
CFI[0x2B] = 0x00
CFI[0x2C] = 0x02 # The number of CFI Erase block regions, found at CFI table �address 0x2C is overridden to 0x1.
CFI[0x2D] = 0x07
CFI[0x2E] = 0x00
CFI[0x2F] = 0x20
CFI[0x30] = 0x00
CFI[0x31] = 0x7E
CFI[0x32] = 0x00
CFI[0x33] = 0x00
CFI[0x34] = 0x01
CFI[0x35] = 0x00
CFI[0x36] = 0x00
CFI[0x37] = 0x00
CFI[0x38] = 0x00
CFI[0x39] = 0x00
CFI[0x3A] = 0x00
CFI[0x3B] = 0x00
CFI[0x3C] = 0x00
CFI[0x40] = 0x50
CFI[0x41] = 0x52
CFI[0x42] = 0x49
CFI[0x43] = 0x31
CFI[0x44] = 0x33
CFI[0x45] = 0x00
CFI[0x46] = 0x02
CFI[0x47] = 0x01
CFI[0x48] = 0x01
CFI[0x49] = 0x04
CFI[0x4A] = 0x00
CFI[0x4B] = 0x00
CFI[0x4C] = 0x01
CFI[0x4D] = 0xB5
CFI[0x4E] = 0xC5
CFI[0x4F] = 0x04
CFI[0x50] = 0x01
CFI[0x51] = 0x00
and i use nios2-flash-programmer command whit arguments --debug --override=over.txt it shows:
# Programming flash with the datafile
"$SOPC_KIT_NIOS2/bin/nios2-flash-programmer" --base=0x00000000 --cable='USB-Blas
ter [USB-0]' --sidp=0x00802010 --id=956946544 --timestamp=1283733585 --instance=
0 -D --override=over.txt "test_flash.flash"
Reading override file "over.txt"
Using cable "USB-Blaster [USB-0]", device 1, instance 0x00
Resetting and pausing target processor: OK
Reading System ID at address 0x00802010: verified
Found CFI table in 16 bit mode
Raw CFI query table read from device:
0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
20: 51 00 52 00 59 00 02 00 00 00 40 00 00 00 00 00 Q.R.Y.....@.....
30: 00 00 00 00 00 00 27 00 36 00 00 00 00 00 07 00 ......'.6.......
40: 07 00 0A 00 00 00 03 00 05 00 04 00 00 00 17 00 ................
CFI query table read from device:
10: 51 52 59 02 00 40 00 00 00 00 00 27 36 00 00 07 QRY..@.....'6...
20: 07 0A 00 03 05 04 00 17 02 00 05 00 02 07 00 20 ...............
30: 00 7E 00 00 01 00 00 00 00 00 00 00 00 00 00 00 .~..............
CFI extended table read from device:
0: 50 52 49 31 33 10 02 01 00 08 00 00 02 B5 C5 02 PRI13...........
10: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
Read autoselect code 0001-007E (in 16 bit mode)
Processing CFI override data from [FLASH-0001-007E]
Override data came from over.txt
Applied override CFI[0x10] = 0x51
Applied override CFI[0x11] = 0x52
Applied override CFI[0x12] = 0x59
Applied override CFI[0x13] = 0x02
Applied override CFI[0x14] = 0x00
Applied override CFI[0x15] = 0x04
Applied override CFI[0x16] = 0x00
Applied override CFI[0x17] = 0x00
Applied override CFI[0x18] = 0x00
Applied override CFI[0x19] = 0x00
Applied override CFI[0x1A] = 0x00
Applied override CFI[0x1B] = 0x27
Applied override CFI[0x1C] = 0x36
Applied override CFI[0x1D] = 0x00
Applied override CFI[0x1E] = 0x00
Applied override CFI[0x1F] = 0x07
Applied override CFI[0x20] = 0x07
Applied override CFI[0x21] = 0x0A
Applied override CFI[0x22] = 0x00
Applied override CFI[0x23] = 0x03
Applied override CFI[0x24] = 0x05
Applied override CFI[0x25] = 0x04
Applied override CFI[0x26] = 0x00
Applied override CFI[0x27] = 0x17
Applied override CFI[0x28] = 0x01
Applied override CFI[0x29] = 0x00
Applied override CFI[0x2A] = 0x00
Applied override CFI[0x2B] = 0x00
Applied override CFI[0x2C] = 0x02
Applied override CFI[0x2D] = 0x07
Applied override CFI[0x2E] = 0x00
Applied override CFI[0x2F] = 0x20
Applied override CFI[0x30] = 0x00
Applied override CFI[0x31] = 0x7E
Applied override CFI[0x32] = 0x00
Applied override CFI[0x33] = 0x00
Applied override CFI[0x34] = 0x01
Applied override CFI[0x35] = 0x00
Applied override CFI[0x36] = 0x00
Applied override CFI[0x37] = 0x00
Applied override CFI[0x38] = 0x00
Applied override CFI[0x39] = 0x00
Applied override CFI[0x3A] = 0x00
Applied override CFI[0x3B] = 0x00
Applied override CFI[0x3C] = 0x00
Applied override CFI[0x40] = 0x50
Applied override CFI[0x41] = 0x52
Applied override CFI[0x42] = 0x49
Applied override CFI[0x43] = 0x31
Applied override CFI[0x44] = 0x33
Applied override CFI[0x45] = 0x00
Applied override CFI[0x46] = 0x02
Applied override CFI[0x47] = 0x01
Applied override CFI[0x48] = 0x01
Applied override CFI[0x49] = 0x04
Applied override CFI[0x4A] = 0x00
Applied override CFI[0x4B] = 0x00
Applied override CFI[0x4C] = 0x01
Applied override CFI[0x4D] = 0xB5
Applied override CFI[0x4E] = 0xC5
Applied override CFI[0x4F] = 0x04
Applied override CFI[0x50] = 0x01
Applied override CFI[0x51] = 0x00
Device size is 8MByte
Erase regions are:
offset 0: 8 x 8K
offset 10000: 127 x 64K
Device supports AMD style programming algorithm
Multi-byte programming not supported
Sector erase timeout is 16s
Word program timeout is 1ms
: Checksumming existing contents
00000000 : Checksum failed - needs erase then program
00002000 : Checksum failed - needs program
00004000 : Checksum failed - needs program
00006000 : Checksum failed - needs program
00008000 : Checksum failed - needs program
0000A000 : Checksum failed - needs program
0000C000 : Checksum failed - needs program
0000E000 : Checksum failed - needs program
00010000 : Checksum failed - needs program
00020000 : Checksum failed - needs program
00030000 : Checksum failed - needs program
00040000 : Checksum failed - needs program
00050000 : Checksum failed - needs program
00060000 : Checksum failed - needs program
00070000 : Checksum failed - needs program
00000000 : Reading existing contents
Checksums took 0.3s
00000000 ( 0%): Erasing
Erased 8kB in 0.0s
00000000 ( 0%): Programming
Program failed
Leaving target processor paused

please help!

Vcbat voltage for cyclonr LS

ajishzacharias — Fri, 03 Sep 2010 10:27:25 GMT

i would like use a cyclone ls 3 series which have operating in put 1.8v and 3.3 v kindly help how much voltage should i have given to vcbat operate safely
with regards ajish

circular buffer

blaiso — Thu, 02 Sep 2010 22:37:14 GMT

hello,

I am trying to realize a circular buffer in verilog, could someone help me?

Odd EPCS Silicon ID Reading

rbn — Thu, 02 Sep 2010 22:21:56 GMT

Hi folks,

When attempting to read the Silicon ID of an EPCS64 flash, I start by sending these four bytes (MSbit first): 0xAB, 0x00, 0x00, 0x00.

I can see that the EPCS64 drives data on the 32nd clock, but what I read is not the expected 0x16, but 0x08. If I read again, I get 0x20, and once more yields 0x82. It turns out that if I keep reading, this pattern repeats itself forever (i.e. 0x08 0x20 0x82 0x08 0x20 0x82...)

Analyzing this a bit further reveals that it's a bitstream with one bit high, five bits low, one bit high, five bits low, etc.

I have absolutely no clue why this happens.

Hope you can help me out here.

Thanks in advance.
Ren� Schipp von Branitz Nielsen