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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity videosync is
port (clk, nRst: in std_logic;
      data: inout std_logic_vector(31 downto 0);
    addr: out std_logic_vector(20 downto 0);
    nCS, nOE, nWE: out std_logic;
    nadsc, nbe0, nbe1, nbe2, nbe3: out std_logic;
    led0, led1, led2, led3: out std_logic;
    flashnOE, flashnCE: out std_logic);
end entity videosync;

architecture behave of videosync is

-- readram signals
  type ramState is (write, read);
  signal ramst : ramState;
  signal ramcount: integer := 0;
  signal notWE: std_logic;
  signal memoryData: std_logic_vector(31 downto 0);
 
begin
 
  readram_process: process (clk, nRst) is
  begin

  if nRst = '0' then
    flashnOE <= '1';
    flashnCE <= '1';
    nadsc <= '1';
    nbe0 <= '1';
    nbe1 <= '1';
    nbe2 <= '1';
    nbe3 <= '1';
    led0 <= '1';
    led1 <= '1';
    led2 <= '1';
    led3 <= '1';
    nCS <= '0';
    nOE <= '1';
    notWE <= '1';
    addr <= (others => '0');
    memoryData <= (others => '0');
    ramcount <= 0;
    ramst <= write;

  elsif rising_edge(clk) then
    case ramst is
   
    when write =>
        if ramcount = 0 then
            addr <= std_logic_vector(to_unsigned(ramcount, 21));
            memoryData <= "11111111000000000000000000000000";
            nadsc <= '0';
            ramcount <= ramcount + 1;

        elsif ramcount = 1 then
            notWE <= '0';
            nadsc <= '1';
            ramcount <= ramcount + 1;
        elsif ramcount = 2 then
            notWE <= '1';
            addr <= (others => '0');
            ramcount <= ramcount + 1;
        else
            ramcount <= 0;
            ramst <= read;
        end if;

    when read =>
            if ramcount = 0 then
                  addr <= std_logic_vector(to_unsigned(0, 21));
                nadsc <= '0';
                ramcount <= ramcount + 1;
            elsif ramcount = 1 then
                nOE <= '0';
                nadsc <= '1';
                if data = "11111111000000000000000000000000" then
                    led0 <= '0';
                else
                    led0 <= '1';
                end if;
                ramcount <= ramcount + 1;
            elsif ramcount = 2 then
                if data = "11111111000000000000000000000000" then
                    led1 <= '0';
                else
                    led1 <= '1';
                end if;
                ramcount <= ramcount + 1;
            elsif ramcount = 3 then
                if data = "11111111000000000000000000000000" then
                    led2 <= '0';
                else
                    led2 <= '1';
                end if;
                ramcount <= ramcount + 1;
                nadsc <= '1';
                addr <= (others => '0');
                nOE <= '1';
            else
                null;
            end if;
    end case;
  end if;

  end process readram_process;
 
 nWE <= '0' when notWE = '0' else '1';
 data    <= memoryData when notWE = '0' else (others => 'Z');

end architecture behave;

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