---

IOWR(ALT_VIP_VFR_0_BASE, 0x3, 0x0);

//

IOWR(ALT_VIP_VFR_0_BASE, 0x4, DISPLAY_MEMORY_BASE);



// frame address in the on chip memory

// 800/1600 - they are the values which work

IOWR(ALT_VIP_VFR_0_BASE, 0x5, 800);

// numbers of reads from master port for whole frame= 40*40*3*8/48 =800 !!!

IOWR(ALT_VIP_VFR_0_BASE, 0x6, 1600);



// number of pixel

IOWR(ALT_VIP_VFR_0_BASE, 0x8, 40);



//

IOWR(ALT_VIP_VFR_0_BASE, 0x9, 40);



//

IOWR(ALT_VIP_VFR_0_BASE, 0x0, 0x1);



// start frame reader
frame_reader_status = IORD(ALT_VIP_VFR_0_BASE, 0x1);

---

Attached Images

	Read.jpg (332.6 KB)
	Write.jpg (341.6 KB)

Just entering a loop in my program which reads the FIFO CSR I get the following which is usual for what is continually repeated.
(Each entry seperated by a few ms)

It seems as if my FIFO isn't deep enough to successfully buffer the large amount of data that is passing through it (its ~8K deep but thats only 8 lines or so on my display), but at 80Mhz shouldnt my SGDMA be sourcing double what the video pipeline can sink, even without the backpressure from the video sync generator?

Attached Images

Untitleddrawing.jpg (32.4 KB)

---

module pixel_converter_565_to_666 (
  input  wire        clk,            // clock.clk
  input  wire        reset,          //      .reset
 
  input  wire [15:0] asi_in0_data,  //  in0.data
  output wire        asi_in0_ready,  //      .ready
  input  wire        asi_in0_valid,  //      .valid
  input  wire        asi_in0_eop,    //    .endofpacket
  input  wire        asi_in0_sop,    //    .startofpacket
  input  wire        asi_in0_empty,  //    .empty
 
  output wire [17:0] aso_out0_data,  //  out0.data
  input  wire        aso_out0_ready, //      .ready
  output wire        aso_out0_valid,  //      .valid
  output wire        aso_out0_eop,  //    .endofpacket
  output wire        aso_out0_sop,  //    .startofpacket
  output wire        aso_out0_empty  //    .empty
 );
 assign asi_in0_ready = aso_out0_ready;
 assign aso_out0_valid = asi_in0_valid;
 assign aso_out0_eop = asi_in0_eop;
 assign aso_out0_sop = asi_in0_sop;
 assign aso_out0_empty = asi_in0_empty;
 assign aso_out0_data[0] = 0;
 assign aso_out0_data[5:1] = asi_in0_data[4:0];
 
 assign aso_out0_data[11:6] = asi_in0_data[10:5];
 
 assign aso_out0_data[12] = 0;
 assign aso_out0_data[17:13] = asi_in0_data[15:11];
 
 // TODO: Auto-generated HDL template
endmodule

---

---

# +-----------------------------------
# | module pixel_converter_565_to_666
# |
set_module_property NAME pixel_converter_565_to_666
set_module_property VERSION 1.1
set_module_property INTERNAL false
set_module_property GROUP ""
set_module_property DISPLAY_NAME pixel_converter_565_to_666
set_module_property TOP_LEVEL_HDL_FILE pixel_converter_565_to_666.v
set_module_property TOP_LEVEL_HDL_MODULE pixel_converter_565_to_666
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property ANALYZE_HDL AUTO
# |
# +-----------------------------------
# +-----------------------------------
# | files
# |
add_file pixel_converter_565_to_666.v {SYNTHESIS SIMULATION}
# |
# +-----------------------------------
# +-----------------------------------
# | parameters
# |
# |
# +-----------------------------------
# +-----------------------------------
# | display items
# |
# |
# +-----------------------------------
# +-----------------------------------
# | connection point clock
# |
add_interface clock clock end
set_interface_property clock ENABLED true
add_interface_port clock clk clk Input 1
add_interface_port clock reset reset Input 1
# |
# +-----------------------------------
# +-----------------------------------
# | connection point in0
# |
add_interface in0 avalon_streaming end
set_interface_property in0 associatedClock clock
set_interface_property in0 symbolsPerBeat 2
set_interface_property in0 dataBitsPerSymbol 8
set_interface_property in0 errorDescriptor ""
set_interface_property in0 maxChannel 0
set_interface_property in0 readyLatency 0
set_interface_property in0 ASSOCIATED_CLOCK clock
set_interface_property in0 ENABLED true
add_interface_port in0 asi_in0_data data Input 16
add_interface_port in0 asi_in0_ready ready Output 1
add_interface_port in0 asi_in0_valid valid Input 1
add_interface_port in0 asi_in0_empty empty Input 1
add_interface_port in0 asi_in0_eop endofpacket Input 1
add_interface_port in0 asi_in0_sop startofpacket Input 1
# |
# +-----------------------------------
# +-----------------------------------
# | connection point out0
# |
add_interface out0 avalon_streaming start
set_interface_property out0 associatedClock clock
set_interface_property out0 symbolsPerBeat 1
set_interface_property out0 dataBitsPerSymbol 18
set_interface_property out0 errorDescriptor ""
set_interface_property out0 maxChannel 0
set_interface_property out0 readyLatency 0
set_interface_property out0 ASSOCIATED_CLOCK clock
set_interface_property out0 ENABLED true
add_interface_port out0 aso_out0_data data Output 18
add_interface_port out0 aso_out0_ready ready Input 1
add_interface_port out0 aso_out0_valid valid Output 1
add_interface_port out0 aso_out0_empty empty Output 1
add_interface_port out0 aso_out0_eop endofpacket Output 1
add_interface_port out0 aso_out0_sop startofpacket Output 1
# |
# +-----------------------------------

---