Altera Forums

Interval Timer Timestamp Problem

quagmyre20 — Fri, 10 Sep 2010 19:18:30 GMT

Hey,

I am trying to determine a baseline time for a particular application and then see what degree of speedup I can obtain my distributing the app across multiple cpus.

I am getting conflicting results when I use the time_stamp API in my program.
When I run the app on a single cpu hardware system, it results in a runtime of appoximately 40 seconds. If I run the same app ON A SINGLE CPU in a 5-cpu hardware system it results in a time of aproximately 15 seconds. This obviously doesn't match up which leads me to believe I'm doing something wrong.

In both SOPC builder designs I've included an interval timer component named cpu0_timer (very creative). I've also set the system library setting "timestamp timer" to that timer component. My code is as basic as timing code gets and matches up with the example given in the altera documentation:

[...]
#include "sys/alt_timestamp.h"
#include "alt_types.h"

int main (void)
{
int time1,time2;
[...]

alt_timestamp_start();

time1 = alt_timestamp();
[...] // do some work
time2 = alt_timestamp();

//print out time2-time1/(ticks/sec)
return 0;

}

I would appreciate some direction or feedback as to what I'm doing wrong. I am using Nios IDE v8.0.
I hope I explained that sufficiently... thanks for the help.

Interval Timer Timestamp Problem

quagmyre20 — Fri, 10 Sep 2010 19:15:44 GMT

[...]
#include "sys/alt_timestamp.h"
#include "alt_types.h"

int main (void)
{
int time1,time2;
[...]

alt_timestamp_start();

time1 = alt_timestamp();
[...] // do some work
time2 = alt_timestamp();

//print out time2-time1/(ticks/sec)

return 0;

}

I would appreciate some direction or feedback as to what I'm doing wrong. I am using Nios IDE v8.0.
I hope I explained that sufficiently... thanks for the help.

Process involved in loading POF file from flash

rawbus — Fri, 10 Sep 2010 19:01:21 GMT

I am currently in the process in trying to make a custom board that has a FPGA. One of the things I want it to do, is to be able to power on and load a POF file without having to be programmed through a computer. I can do this on the development boards using the parallel flash loader megafunction component. However, I'm confused in the steps I need to follow in order to make this happen in my custom board.

I have the CFI flash device and I have the JTAG pins and I have the FPGA, but I don't understand how upon applying power the FPGA will try to grab the programming file from the flash memory. I know that the dev kits all use the CPLD to do this function, so do I need to use a CPLD as well?

This is my first time trying to make a custom board and I've had trouble finding app notes that talk about this specifically. I'm assuming that getting the programming file to the flash memory is the same process described in the guide under programming the flash device. All the information I've read seems to lead me in the direction that I would need a CPLD to do this but I haven't been able to find a black and white answer explaining this process.

IORD IOWR macros vs. memory access to peripherals

basafran — Fri, 10 Sep 2010 18:05:45 GMT

What is the point of the IORD and IOWR macros? I can access my custom Avalon peripherals using them, but it seems like I can't access them like the following:

volatile alt_u32 *DEV_PTR = DEV_0_BASE;
alt_u32 data_in = 0;

data_in = DEV_PTR[0];

However, I CAN access the Altera CFI flash memory peripheral using the simple memory access method shown above and read my flash! I do not understand the distinctions. I do understand that the macros avoid the cache.

Thanks!

How to load the sdf file to Modelsim?

li_polaris — Fri, 10 Sep 2010 17:06:09 GMT

How to import the SDF File to the Modelsim to achieve the timing simulation with the Quartus II and Modelsim?

thank you in advance!

Beginner --

OPTOGAL — Fri, 10 Sep 2010 17:03:51 GMT

I have the Nios II development kit Cyclone IIEP2C35. I have downloaded the the free web ver. of Quartus 10. The install didn't come with the example that is explained on the getting started users guide. I looked everywhere but was unable to find it. Does anyone know where I can download this prototype or may be know somewhere else where I can look for an easy/beginner type examples to learn with?...Totally new, but excited to figure this thing out.

Your help is greatly appreciated

Thank you.

Arria II GX DDR2 issues with .QSF file

pinscore — Fri, 10 Sep 2010 17:00:23 GMT

I have been banging my head against a wall for the last day and I hope I can get a solution to this.

Challenge:
Generated a HPCII DDR2 controller using the Megawizard, not an issue. The top level of the project with the controller is synthesizing fine including the controller. The problem comes with the DQSN signal in the qsf file. Here are the assignment statements in the qsf file:

#
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to MEM_DQS
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MEM_DQS
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to MEM_DQSN
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to MEM_DQSN
set_location_assignment PIN_AM25 -to MEM_DQS[0]
set_location_assignment PIN_AM26 -to MEM_DQSN[0]
set_instance_assignment -name OUTPUT_ENABLE_GROUP 57199071 -to MEM_DQS
set_instance_assignment -name OUTPUT_ENABLE_GROUP 57199071 -to MEM_DQSN
set_instance_assignment -name IO_STANDARD "SSTL-18 CLASS I" -to MEM_DQS[0]
#

These statements are essentially a copy from the golden qsf file from the ARRIA II GX devbrd kit. During fitting I get this message:

Error: Can't place node "MEM_DQSN[0]" -- node is a differential I/O node

I have tried multiple changes to these statements and nothing is working.

Ideas?

pinscore

Clean .pof file for 7032SLC44?

supercruise — Fri, 10 Sep 2010 16:17:34 GMT

How can I get a clean (erased) .pof file for an EPM7032SLC44 device? Beyond buying a brand new device, which are really hard to find.

I bought a bunch of surplus 7032SLC devices that have had their JTAG pins programmed as I/O so they can't be re-programmed via JTAG.

Thanks in advance.

Gate-level Simulation

FPGA_expert — Fri, 10 Sep 2010 14:19:51 GMT

Hi ,

I am working on a design , it has a top level VHDL file ( a main state machine in it) and then a UART is enabled from this Main ( State machine ) .
Everything works fine in RTL simulation . But when i switch to Gate-level Simulation i dont see any response or even glitch when UART is enabled .

This is using Quartus-II ver 10.0 and Altera-Modelsim .

When i compiled the design in Xilinx , again it failed in Gate-level but before shutting down it spite out a message about Modelsim couldnt handle 10K lines of code .

Any clues ???

Thanks in advance.

Please help me to identify device.

waveform — Fri, 10 Sep 2010 12:44:13 GMT

We got our newly designed instrument with altera device istalled on it: Stratix III EP3SL50F780C2N. See this picture:

I turn this device on and read with JTAG device code. See next picture:

Here is two unconformities:
1) Device marked as "Startix(tm)", although it must be marked as "Stratix(tm) III".
2) JTAG reads code EP3SE50, although device is marked as EP3SL50.

Please, help me to identify, is it a native altera manufactered device or it may be a re-marked or tampered with to represent a different device or counterfeit?

timing Analyzer

catmoe88 — Fri, 10 Sep 2010 11:45:27 GMT

i get the message : " Critical Warning: Timing requirements for slow timing model timing analysis were not met. See Report window for details."
Failed paths: 768 , slack-265ns. what can i do against this?

how to run batch mode in QuartusII

liguoq — Fri, 10 Sep 2010 09:17:09 GMT

I want to run some batch command in QuartusII, but the sample QuartusII command is fail to run:
> quartus_sh --qhelp

/opt/quartusII_10.0_local/quartus/bin/quartus_sh: SCRIPT_PATH=/opt/quartusII_10.0_local/quartus/bin: is not an identifier

how to deal with it?

nano-X problem

mr_DK — Fri, 10 Sep 2010 08:38:20 GMT

Hello everyone,

I wanted to ask a little question on the forum about nano-X. I followed the complete tutorial on the nios wiki for the Framebuffer, but everytime I try to start "nano-X &" I get the following syntax error:

Code:

[NiosII EDS]$ nios2-terminal

nios2-terminal: connected to hardware target using JTAG UART on cable

nios2-terminal: "USB-Blaster [USB 7-1.1]", device 1, instance 0

nios2-terminal: (Use the IDE stop button or Ctrl-C to terminate)



Linux version 2.6.34-00701-gc130879-dirty (hacor@localhost.localdomain) (gcc version 4.1.2) #150 Fri Sep 10 10:25:37 CEST 2010

bootconsole [early0] enabled

early_console initialized at 0xe8002000





Linux/Nios II-MMU

init_bootmem_node(?,0x5d2, 0x0, 0x2000)

free_bootmem(0x5d2000, 0x1a2e000)

reserve_bootmem(0x5d2000, 0x400)

Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 8128

Kernel command line: 

PID hash table entries: 128 (order: -3, 512 bytes)

Dentry cache hash table entries: 4096 (order: 2, 16384 bytes)

Inode-cache hash table entries: 2048 (order: 1, 8192 bytes)

We have 8192 pages of RAM

Memory available: 26516k/5959k RAM, 0k/0k ROM (1360k kernel code, 4598k data)

Hierarchical RCU implementation.

NR_IRQS:32

Console: colour dummy device 80x25

Calibrating delay loop... 48.94 BogoMIPS (lpj=244736)

Mount-cache hash table entries: 512

init_BSP(): registering device resources

bio: create slab  at 0

Switching to clocksource timer

JFFS2 version 2.2. (NAND) � 2001-2006 Red Hat, Inc.

msgmni has been set to 51

Block layer SCSI generic (bsg) driver version 0.4 loaded (major 254)

io scheduler noop registered

io scheduler deadline registered

io scheduler cfq registered (default)

fb0: Altera FB frame buffer device

ttyJ0 at MMIO 0x8002000 (irq = 10) is a Altera JTAG UART

console [ttyJ0] enabled, bootconsole disabled

console [ttyJ0] enabled, bootconsole disabled

physmap platform flash device: 01000000 at 04000000

physmap-flash.0: Found 1 x16 devices at 0x0 in 16-bit bank

 Intel/Sharp Extended Query Table at 0x010A

 Intel/Sharp Extended Query Table at 0x010A

 Intel/Sharp Extended Query Table at 0x010A

 Intel/Sharp Extended Query Table at 0x010A

 Intel/Sharp Extended Query Table at 0x010A

Using buffer write method

Using auto-unlock on power-up/resume

cfi_cmdset_0001: Erase suspend on write enabled

RedBoot partition parsing not available

Using physmap partition information

Creating 4 MTD partitions on "physmap-flash.0":

0x000000d00000-0x000001000000 : "romfs/jffs2"

0x000000000000-0x000000020000 : "catalog"

0x000000180000-0x000000d00000 : "application"

0x000000020000-0x000000180000 : "selector"

Freeing unused kernel memory: 4200k freed (0xc0155000 - 0xc056e000)

ifconfig: socket: Function not implemented

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For further information check:

http://www.uclinux.org/







BusyBox v1.16.2 (2010-09-07 22:27:30 CEST) hush - the humble shell

Enter 'help' for a list of built-in commands.



root:/> nano-X &

[1] 690 nano-X

root:/> sh: syntax error at '�



nios2-terminal: exiting due to ^D on remote

~

[NiosII EDS]$ nios2-terminal

nios2-terminal: connected to hardware target using JTAG UART on cable

nios2-terminal: "USB-Blaster [USB 7-1.1]", device 1, instance 0

nios2-terminal: (Use the IDE stop button or Ctrl-C to terminate)



 

[1] Done                   nano-X

root:/> nanowm &

[1] 695 nanowm

root:/> sh: syntax error: unexpected )

I tried the tutorial with the neek_Web_server example design and with my custom design, both gave the same results. nios2-terminal automatically exits after giving the syntax error... I'm sure the hardware designs are ok, because when I follow the tutorial to show the console on the neek LCD, it works perfectly.

I did the following steps:

-in the uClinux-dist/user/microwin/src/ I did "make clean" and make, which worked perfectly.
- in the uClinux-dist/ I did "make"

I'm working on this problem for 4 days now, and it's really bothering me. Any help would really be appreciated.

Thanks!

Best,

Hans

RTL Viewer, group into buses

leonidas — Fri, 10 Sep 2010 08:28:00 GMT

I want to use the quartus II RTL-Viewer for documentation purposes, i.e. i want it to create a schematic with corresponding wiring of all the entities i have in my design.
Basically it also works, the only thing is that it expands all records and arrays of the connecting signals, so that in the end all wires in the diagramm represent just one bit.
Needless to say, this makes the schematic very unclear.
However, in the manual for the rtl-viewer it is written that the rtl-viewer actually should be able to group pins and wires into buses "where appropriate". Unfortunately, i could not find any information how to get this feature to work.
Does anybody know how to get the rtl-viewer to display buses properly?

Modelsim waveform : DO NOT SHOW glitches

veejain — Fri, 10 Sep 2010 06:31:30 GMT

Hi,

Is there a setting in Modelsim waveform viewer by which we can disable/enable display of glitches?? I know there are glitches in my design and it is acceptable. I just do not want see it in the waveform.

Thanks
Vinay

Problem with SOPC builder

burnaws — Fri, 10 Sep 2010 03:42:45 GMT

Hi there,
I got a problem when I try to run the demo for the DE2_NIOS_DEVICE_LED. When I try to run the SOPC builder it gives me this error:

Error: ISP1362.avalon_slave_1_irq: associatedAddressablePoint out of range

Is there anyone can help me on this problem?

cheers.

PCI-Express-HIP-MegaWizard: BFM driver modules

Rafael Grabowski — Thu, 09 Sep 2010 22:38:13 GMT

Hi,

I want to generate a PCI-Express HIP with the MegaWizard Plugin Manager. The PCI Express Compiler User Guide tells, that the MegaWizard should also generate BFM driver modules (location of the Root Port BFM is: _examples/rootport/testbench/altpcietb_bfm_driver_rp.v).

But the testbench directory doesn't exist in the rootport directory!

Can anybody please tell me, where I can find, or how I can generate the BFM driver module "altpcietb_bfm_driver_rp.v"?!

Regards,

Rafael Grabowski

Problem with Modelsim altera starter edition

dar89 — Thu, 09 Sep 2010 20:45:43 GMT

Hello,i can't execute Modelsim altera starter edition (i've tried with versions 6.5b for quartus 9.1 sp1 and sp2,but it however doesn't work!).When I open the program (obviously after I have installed the program) appear the following window(paste in the browser):
img835.imageshack.us/img835/6084/immagineerr.jpg

I've tried on two different pc,but the error is the same.Can anybody help me?
Sorry for me english!

Thanks!

PIO or Custom Component?

tscodeca — Thu, 09 Sep 2010 19:30:18 GMT

I'm starting a design with the SOPC (NIOS) and I cant decide if I should put my signal processing functionality outside the SOPC (and use the PIO) OR create a custom component and put it in the SOPC.

The signal processing is pretty intense but there are a lot of parameters that have to be passed from the NIOS which would make the PIO a hassle. I cant find anything in the documentation that contrasts the two methods. Im' leaning towards the custom component b/c it seems cleaner but I would hate to get far into it and find out that it wont work in the SOPC.

What are the big differences between the two methods (functionally speaking)? Any words of wisdom would be appreciated.

Differential clock outputs from Cyclone II - How to assign

cgregory — Thu, 09 Sep 2010 19:01:29 GMT

Is there a way (using Quartus) to output a differential clock from a Cyclone II PLL without getting the "Warning: ... Use PLL dedicated clock outputs to ensure jitter performance" message?

I have assigned the two pins for output to the adjacent PLLn_OUTp and PLLn_OUTn pins. Connecting these pins to the PLL "c0" output, with an inverter on one, results in the usual warning for the inverted pin. Examining the floorplan shows that the inverted signal is routed clear across the chip, and then back.

The ALTIOBUF_OUT megafunction is grayed out in the megawizard (not applicable to Cyclone II?). ALTOUTBUF_DIFF is not grayed out, but generates an error (not allowed for this device type).

There ought to be a way....

Thanks!
Carl